1. Field of the Invention
The present invention relates to semiconductor devices. Specifically, it relates to: a Cu alloy for semiconductor interconnections; a method for fabricating interconnections containing the Cu alloy; a semiconductor device having Cu alloy interconnections fabricated by the method; and a sputtering target for fabricating Cu alloy interconnections for semiconductors.
2. Description of the Related Art
Semiconductors have had higher and higher performance and must operate faster with higher packaging densities. For faster operation of semiconductors, it is effective to reduce electric resistances of interconnection films as much as possible, since high electric resistances cause delay of signal transmission. For this purpose, copper or a copper alloy (hereinafter referred to as “Cu-based metal”) is replacing aluminum or an aluminum alloy (hereinafter referred to as “Al-based metal”) as the material for interconnection films. In addition, the width of interconnections (hereinafter briefly referred to as “interconnection width”) is preferably reduced as much as possible for enabling faster operation. The interconnection width of semiconductors has been frequently about 0.25 μm but is more and more reduced in recent years.
For larger packaging densities, interconnections are designed to have a multilayer structure, for example, by a damascene interconnection process. In the damascene process, for example, an interlayer dielectric film typically of silicon oxide is deposited on a semiconductor substrate; interconnection patterns such as grooves for embedding interconnections and holes (trenches and via holes) for connecting interconnections (hereinafter such grooves and holes are generically referred to as “grooves”) are fabricated in the interlayer dielectric film; a barrier film is then deposited by sputtering; a Cu-based metal is embedded in the grooves by electroplating; and excess Cu-based metal is removed by chemical mechanical polishing (CMP) to yield interconnections. After polishing, another dielectric film is fabricated on the surface of the polished article, and the above-mentioned processes are repeated to yield multilayer interconnections.
If the grooves have large widths (namely, the interconnection width is large), a Cu-based metal can be easily embedded in the grooves by electroplating. A reducing interconnection width of semiconductors, however, inevitably induces reducing widths of grooves. Consequently, the Cu-based metal is not sufficiently embedded in the grooves and thereby fails to fabricate interconnections.
Japanese Unexamined Patent Application Publication No. 11-260820 proposes a technique for embedding a Cu-based metal in grooves (refer to claims, [0011], [0013], [0020], and [0028]) This technique is a method for embedding a copper based interconnection film under pressure. In the method, a surface of dielectric film of a substrate having holes or grooves is covered with a copper based material for interconnection films by physical vapor deposition; a gas at a high pressure and a temperature equal to or lower than the melting point of the material for interconnection films is allowed to act to make the material for interconnection films plastically flow or diffuse into the holes or grooves. The document described that film deposition by physical vapor deposition is carried out at elevated temperatures of the target member of about 200° C. to about 400° C., and then embedment by high-pressure gas is carried out. As a result of investigations by the present inventors, however, the copper-based material for interconnection films may not be embedded in the holes or grooves with decreasing widths of the holes or grooves. This technique is therefore susceptible to improvement. The document mentions a copper-based material for interconnection films mainly containing Cu and containing Sb as an alloying element. However, there is no example of such a material containing Sb, and the document fails to practically teach effects of the addition of Sb.